1. Field of the Invention
This invention relates to synchronous semiconductor storage devices of an address multiplex type, which operate in synchronization with clock signals given from the external.
This application is based on Patent Application No. Hei 11-16273 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, dynamic random-access memories (i.e., DRAMs) are normally used for main storage of computers and are continuously improved in high-speed performance. However, operating speeds of the DRAMs cannot catch up with operating speeds of microprocessors whose performance is improved more and more in these days. For this reason, access times and cycle times of the DRAMs bottleneck further improvement of computer systems. So, there is a problem in which performance of the computer systems as a whole should be reduced due to the access times and cycle times of the DRAMs. In these days, the computer systems tend to use synchronous DRAMs (or SDRAMs), which operate in synchronization with clock signals, as DRAMs applicable to the microprocessors which operate at high speeds. For example, Japanese Patent Application, Publication No. Hei 10-504129 (which corresponds to PCT International Publication No. WO 96/29637, hereinafter, simply referred to as a related art) discloses an example of a synchronous DRAM with programmable latency period.
FIG. 7 is a block diagram showing a configuration of a synchronous DRAM, which is designed in consideration of the aforementioned related art. As compared with an original configuration of the synchronous DRAM of the related art, the configuration of the synchronous DRAM of FIG. 7 is modified to cope with a configuration of the present invention, details of which will be described later. Incidentally, the specifics of the configuration of the synchronous DRAM will be described later in connection with embodiments of the present invention, so only the selected parts of FIG. 7 are discussed below in connection with problems.
FIGS. 8A-8H and FIGS. 9A-9H are time charts, which are used to show timings in read operations of the synchronous DRAM shown in FIG. 7. In those figures, signals and data corresponding to those shown in FIG. 7 are designated by same reference symbols and numerals. FIG. 7 shows a number of reference symbols such as "/CS" and "nACT", each of which is expressed using a symbol "/" or a character "n" as its top to represent a negative logic. That is, each signal or data having a negative logic is denoted by a reference symbol whose top corresponds to "/" or "n".
Specifically, FIGS. 8A, 9A show a clock signal CLK, which is given from the external (i.e., external system or device) of the synchronous DRAM. FIGS. 8B, 9B show commands "Com." which are given from the external to designate various instructions for the synchronous DRAM. FIGS. 8C, 9C show an address signal "Aj" (where j is an integer which is not less than 0) which is given from the external. FIGS. 8E, 9E show a control signal .phi.2, which is made valid every time a column address Yj (see FIGS. 8G, 9G) for accessing a memory cell array 22 consisting of rows and columns is generated. FIGS. 8F, 9F show a column address control signal .phi.3, which controls timing for instructing a column address buffer 18 to output the column address Yj to a column decoder 23. FIGS. 8D, 9D show a signal C46, which instructs the synchronous DRAM whether to directly output the control signal .phi.2 as the column address control signal .phi.3 or whether to generate the column address control signal .phi.3 by delaying the control signal .phi.2 by a predetermined time. FIGS. 8H, 9H show output data DQk which are read from the synchronous DRAM. At a write operation mode, data being input to the synchronous DRAM are given as the output data DQk. The commands Com. (see FIGS. 8B, 9B) contain a variety of commands such as "READ" and "ACT". Herein, "READ" designates a read command, which instructs the synchronous DRAM to perform a burst read operation from the memory cell array 22, while "ACT" designates an active command for activating a row whose address is designated by the address signal Aj.
In the aforementioned synchronous DRAM, a time by which output data appear as DQk after an active command ACT is counted using units of cycles of the clock signal CLK. So, a number of cycles corresponding to the above time is called "row address strobe (RAS) latency". In addition, a time by which output data appear as DQk after a read command READ is counted using units of cycles of the clock signal CLK. So, a number of cycles corresponding to the above time is called "column address strobe (CAS) latency". According to the specification of the synchronous DRAM, if CAS latency is "N" (where "N" is a natural number), its corresponding RAS latency is "2N". Because, a time by which a read command READ is ready to be applied after an active command ACT is applied to the synchronous DRAM is substantially identical to a time by which the synchronous DRAM outputs data after the read command READ. Incidentally, it is possible to further describe the aforementioned time corresponding to the RAS latency in detail, as follows:
An active command ACT is applied to the synchronous DRAM, so that a specific word line "Word" is selected. Then, data regarding the word line Word in the memory cell array 22 are amplified by a sense amplifier 24 and are ready to be read out. So, the time of the RAS latency is defined between the timing to apply the active command ACT and the timing that the data are ready to be read out.
In the following description, the time of the RAS latency is denoted by "tRCD", while the time of the CAS latency is denoted by "tAA". In addition, a time "tRAC" is defined as a sum of the above times, i.e., tRAC=tRCD+tAA.
Next, an outline operation of the synchronous DRAM within the time tRCD will be described below.
First, a row address Xj output from a row address buffer 17 is supplied to a row decoder 21 by way of a pre-decoder latch 20. The row decoder 21 decodes the row address Xj so as to activate any one of word lines (Word) on the memory cell array 22. Then, data regarding the activated word line Word corresponding to the row address Xj are input to a sense amplifier 24 in which the data are amplified.
Next, an outline operation of the synchronous DRAM within the time tAA after the time tRCD, will be described below.
A column address Yj output from a column address buffer 18 is decoded by a column decoder 23, so that a corresponding column switch (YSW) is activated (or turned on). As a result, data being activated by the column switch YSW, corresponding to the column address Yj, within the data being amplified by the sense amplifier 24 are supplied to a data amplifier 25 by way of a read bus Rbus, wherein the data are amplified. Then, the data are supplied to a data amplifier 28 by way of a data bus R/Wbus, wherein the data are further amplified. The data being amplified by the data amplifier 28 are transferred to a data latch 29 at a timing that a signal C27 is validated. Thereafter, when an output clock signal ICLKOE is validated, the data transferred to the data latch 29 are output as data DQk by way of an output buffer 30.
The performance of the synchronous DRAMs in mass production meet specification of tRCD=20 ns, tAA=16 ns (where "ns" denotes unit of nanosecond). Therefore, if a setup time of 4 ns is required for the system to which the synchronous DRAM is applied, it is possible to calculate the aforementioned latencies, under the condition where the clock signal CLK has a frequency of 100 MHz (i.e., clock cycle of 10 ns), as follows: EQU RAS latency=(20+16+4)/10=4 EQU CAS latency=(16+4)/10=2
In addition, further improvement of performance is realized using the forefront process, by which some engineers (or manufacturer) develop high-performance products of synchronous DRAMs, which are capable of operating with the aforementioned latencies and with a higher clock frequency (CLK) of 133 MHz (i.e., clock cycle of approximately 7.5 ns). FIGS. 8A-8H show operation timings of the high-performance product of the synchronous DRAM, wherein tRAC=27 ns, tRCD=15 ns, tAA=12 ns. Herein, at time t101, an active command ACT and a row address R1 are applied to the synchronous DRAM. At time t102, a read command READ and a column address C1-1 are applied to the synchronous DRAM. Thereafter, at time t110 which is four cycles after the time t101(ACT), the synchronous DRAM outputs data Q1-1, designated by the row address R1 and column address C1-1, on the memory cell array 22. Hence, the RAS latency is "4". In addition, the synchronous DRAM outputs the data Q1-1 at the time t110 which is two cycles after the time t102(READ). Hence, the CAS latency is "2".
Another system whose clock frequency is lower than the aforementioned one (see FIGS. 8A-8H) is designed to optimize the time tAA by programming "small" CAS latency. For example, FIGS. 9A to 9H show operation timings of the synchronous DRAM, which is produced using the forgoing forefront process and which operates with the clock frequency of 100 MHz (i.e., clock cycle of 10 ns), wherein tRAC=26 ns, tAA=16 ns. In that case, it is optimal to employ the setting in which the RAS latency is set at "3" while the CAS latency is set at "2". However, such setting brings strict situation in which tRCD=10 ns, tAA=16 ns. That is, the time tAA may have a room in adjustment, however, the time tRCD is strictly restricted. This remarkably deteriorates speed derivative ratios.
In order to avoid problems described above, the aforementioned related art proposes a method in which when the time tRCD is a critical parameter, the time tAA is compensated with the time tRCD by delaying designation of the column address Yj. That is, in the case of FIGS. 8A-8H where the clock frequency (CLK) is 133 MHz, the RAS latency is "4", and the CAS latency is "2", the time tRCD is very long so that the burst control circuit 49 does not control the column address control signal .phi.3 to be delayed from the control signal .phi.2. For this reason, in the case of FIGS. 8A-8H, the column address control signal .phi.3 is output at time t104 just after time t103 when the control signal .phi.2 is generated. In contrast to the above, in the case of FIGS. 9A-9H where the RAS latency is "3" and the CAS latency is "2", the time tAA is compensated with the time tRCD. In this case, the synchronous DRAM uses a wait time delay circuit (not shown), equipped inside of the burst control circuit 49, to control the column address control signal .phi.3 to be delayed from the control signal .phi.2. Therefore, in the case of FIGS. 9A-9H, the column address control signal .phi.3 is output at time t133, which is delayed by a predetermined time from time t132 when the control signal .phi.2 is generated.
The aforementioned related art does not at all disclose any means or measures to change over activation and inactivation for the wait time delay circuit. Even if the related art employs the configuration of the synchronous DRAM shown in FIG. 7, the synchronous DRAM itself cannot make determination as to whether the column address control signal .phi.3 is delayed from the control signal .phi.2 or not. In order to make such determination, it is necessary to perform programming from the external of the synchronous DRAM. That is, the related art may be designed such that a mode register 46 is set with data (or commands) regarding determination as to whether the column address control signal .phi.3 is directly derived from the control signal .phi.2 or the column address control signal .phi.3 is created by delaying the control signal .phi.2. That is, the mode register 46 outputs a signal C46 to the burst control circuit 49. In accordance with the signal C46, the burst control circuit 49 determines whether to delay the control signal .phi.2 and generates the column address control signal .phi.3. Therefore, in the case of FIGS. 8A-8H, the signal C46 is fixed at a low level (or L level) (see FIG. 8D), so that the column address control signal .phi.3 is created without delaying the control signal .phi.2. In the case of FIGS. 9A-9H, the signal C46 is fixed at a high level (or H level), so that the column address control signal .phi.3 is created by delaying the control signal .phi.2.
As described above, the related art requests the system to perform the programming regarding the RAS latency, which is not originally included in the standard(s) of the synchronous DRAM in these days. In other words, the related art provides the synchronous DRAM with necessity that special standard is set to the synchronous DRAM from the external. In addition, the related art must determine clock frequencies in response to RAS latencies in advance respectively for first case where the time tRCD is sufficient and second case where the time tRCD is insufficient. So, it is necessary to set different delay times for the wait time delay circuit, provided inside of the burst control circuit 49, in response to differences between times tRCD and tAA. Further, in order to cope with a higher clock frequency which is higher than the foregoing clock frequencies in the foregoing cases of FIGS. 8A-8H and FIGS. 9A-9H and in which RAS latency is "5" and CAS latency is "3", for example, a ratio between times tRCD and tAA should differ from ratios of the foregoing cases. This inevitably makes the delay time to be different from the foregoing cases. In short, the related art lacks means (or device) for detecting a relationship between the times tRCD and tAA, so it is necessary to set a different delay time with respect to each latency. This makes designing of the synchronous DRAM to be complicated.
In general, the time tRCD has several dependencies such as process dependency, source voltage dependency and temperature dependency. Hence, in the simulation which is effected when designing the RAS latency and CAS latency, it is necessary to consider various parameters containing the temperature coefficient of the time tRCD. If the time tRCD is reduced from two cycles (see FIGS. 8A-8H) to one cycle (see FIGS. 9A-9H), the related art may design the delay time based on a time of "tRCD--(one clock cycle)". It may be relatively easy to set the same temperature coefficient of the time tRCD with respect to the delay time. However, it is difficult to set the temperature coefficient in response to the time, which is calculated by subtracting a fixed time of one clock cycle from the time tRCD. This causes an extra time being required for the simulation. In addition, it is difficult to perform the simulation with good accuracy.